Data flow graph dominant designs, such as communication video and audio applications, are common in today’s IC industry. In these designs, the datapath resources (e.g., adders,...
In this paper, we present a new method to the built-in selftestable data path synthesis based on integer linear programming (ILP). Our method performs system register assignment, ...
This paper proposes two very fast graph theoretic heuristics for the low power binding problem given fixed number of resources and multiple architectures for the resources. First...
In deep submicron technology, wire delay is no longer negligible and is gradually dominating the system latency. Some state-of-the-art architectural synthesis flows adopt the distr...
The IA-64 architecture has been designed as a synthesis of VLIW and superscalar design principles. It incorporates typical functionality known from embedded processors as multiply...