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ISCAS
2003
IEEE
103views Hardware» more  ISCAS 2003»
13 years 10 months ago
An ILP-based scheduling scheme for energy efficient high performance datapath synthesis
Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappi...
VLSID
2003
IEEE
92views VLSI» more  VLSID 2003»
14 years 5 months ago
Energy Efficient Scheduling for Datapath Synthesis
In this paper, we describe two new algorithms for datapath scheduling which aim at energy reduction while maintaining performance. The proposed algorithms, time constrained and re...
Saraju P. Mohanty, N. Ranganathan
EUC
2006
Springer
13 years 8 months ago
Dynamic Repartitioning of Real-Time Schedule on a Multicore Processor for Energy Efficiency
Multicore processors promise higher throughput at lower power consumption than single core processors. Thus in the near future they will be widely used in hard real-time systems as...
Euiseong Seo, Yongbon Koo, Joonwon Lee
CF
2005
ACM
13 years 6 months ago
An efficient wakeup design for energy reduction in high-performance superscalar processors
In modern superscalar processors, the complex instruction scheduler could form the critical path of the pipeline stages and limit the clock cycle time. In addition, complex schedu...
Kuo-Su Hsiao, Chung-Ho Chen
MSS
2007
IEEE
109views Hardware» more  MSS 2007»
13 years 11 months ago
GreenStor: Application-Aided Energy-Efficient Storage
The volume of online data content has shown an un­ precedented growth in recent years. Fueling this growth are new federal regulations which warrant longer data re­ tention and ...
NagaPramod Mandagere, Jim Diehl, David Hung-Chang ...