1079 search results - page 2 / 216 » An Implementation of an Address Generator Using Hash Memorie... |
ISCAS
1994
IEEE
13 years 9 months ago
1994
IEEE
This paper presents a novel VLSI architecture for high-speed data compressor designs which implement the well-known LZ77 algorithm. The architecture mainly consists of three units...
DATE
2004
IEEE
13 years 9 months ago
2004
IEEE
Tile-based data layout has been applied to achieve various objectives such as minimizing cache conflicts and memory row switching activity. In some applications of tilebased mappi...
ANCS
2009
ACM
13 years 3 months ago
2009
ACM
As the Internet grows, both the number of rules in packet filtering databases and the number of prefixes in IP lookup tables inside the router are growing. The packet processing e...
SIGMETRICS
1991
ACM
13 years 9 months ago
1991
ACM
Prior to this work, all implementations of stack simulation [MGS70] required more than linear time to process an address trace. In particular these implementations are often slow ...
PE
2000
Springer
13 years 5 months ago
2000
Springer
Conventional methods for state space exploration are limited to the analysis of small systems because they suffer from excessive memory and computational requirements. We have dev...