25 search results - page 2 / 5 » An O(n) Algorithm for Transistor Stacking with Performance C... |
ICCAD
2007
IEEE
14 years 2 months ago
2007
IEEE
— In this paper, we present the first work on the Steiner routing for 3D stacked ICs. In the 3D Steiner routing problem, the pins are located in multiple device layers, which ma...
ICCAD
2009
IEEE
2009
IEEE
An efficient wakeup scheduling considering resource constraint for sensor-based power gating designs
13 years 3 months ago
Power gating has been a very effective way to reduce leakage power. One important design issue for a power gating design is to limit the surge current during the wakeup process. N...
RTAS
2007
IEEE
14 years 20 hour ago
2007
IEEE
Using preemption threshold scheduling (PTS) in a multi-threaded real-time embedded system reduces system preemptions and hence reduces run-time overhead while still ensuring real-...
DATE
2008
IEEE
14 years 6 days ago
2008
IEEE
Leakage power is a serious concern in nanometer CMOS technologies. In this paper we focus on leakage reduction through automatic insertion of sleep transistors for power gating in...
MOBIHOC
2007
ACM
14 years 5 months ago
2007
ACM
Recently, there has been substantial interest in the design of crosslayer protocols for wireless networks. These protocols optimize certain performance metric(s) of interest (e.g....