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VLSID
2007
IEEE
108views VLSI» more  VLSID 2007»
14 years 5 months ago
Soft Error Rate Analysis for Combinational Logic Using An Accurate Electrical Masking Model
Accurate electrical masking modeling represents a significant challenge in soft error rate analysis for combinational logic circuits. In this paper, we use table lookup MOSFET mode...
Feng Wang 0004, Yuan Xie, R. Rajaraman, Balaji Vai...
TON
2002
83views more  TON 2002»
13 years 4 months ago
MLSR: a novel routing algorithm for multilayered satellite IP networks
Several IP-based routing algorithms have been developed for low-Earth orbit (LEO) satellite networks in recent years. The performance of the satellite IP networks can be improved d...
Ian F. Akyildiz, Eylem Ekici, Michael D. Bender
ISCA
1997
IEEE
120views Hardware» more  ISCA 1997»
13 years 9 months ago
Run-Time Adaptive Cache Hierarchy Management via Reference Analysis
Improvements in main memory speeds have not kept pace with increasing processor clock frequency and improved exploitation of instruction-level parallelism. Consequently, the gap b...
Teresa L. Johnson, Wen-mei W. Hwu
DAC
2006
ACM
14 years 6 months ago
Statistical logic cell delay analysis using a current-based model
A statistical model for the purpose of logic cell timing analysis in the presence of process variations is presented. A new current-based cell delay model is utilized, which can a...
Hanif Fatemi, Shahin Nazarian, Massoud Pedram
PLDI
2003
ACM
13 years 10 months ago
A compiler framework for speculative analysis and optimizations
Speculative execution, such as control speculation and data speculation, is an effective way to improve program performance. Using edge/path profile information or simple heuristi...
Jin Lin, Tong Chen, Wei-Chung Hsu, Pen-Chung Yew, ...