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» An SLA perspective on the router buffer sizing problem
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INFOCOM
1998
IEEE
13 years 9 months ago
Doubling Memory Bandwidth for Network Buffers
Memory bandwidth is frequently a limiting factor in the design of high-speed switches and routers. In this paper, we introduce a buffering scheme called ping-pong buffering, that ...
Youngmi Joo, Nick McKeown
MICRO
2003
IEEE
161views Hardware» more  MICRO 2003»
13 years 10 months ago
Design and Implementation of High-Performance Memory Systems for Future Packet Buffers
In this paper we address the design of a future high-speed router that supports line rates as high as OC-3072 (160 Gb/s), around one hundred ports and several service classes. Bui...
Jorge García-Vidal, Jesús Corbal, Ll...
SIPS
2007
IEEE
13 years 11 months ago
Dynamic Channel Flow Control of Networks-on-Chip Systems for High Buffer Efficiency
System-on-Chip (SoC) designs become more complex nowadays. The communication between each processing element often suffers challenges due to the wiring problem. Networks-on-Chip (...
Sung-Tze Wu, Chih-Hao Chao, I-Chyn Wey, An-Yeu Wu
GLOBECOM
2009
IEEE
13 years 11 months ago
Emulation of Optical PIFO Buffers
—With recent advances in optical technology, we are closer to building all-optical routers than ever before. A major problem in this area, however, is the lack of all-optical mem...
Houman Rastegarfar, Monia Ghobadi, Yashar Ganjali
ICC
2007
IEEE
13 years 11 months ago
Power Managed Packet Switching
— High power dissipation in packet switches and routers is fast turning into a key problem, owing to increasing line speeds and decreasing chip sizes. To address this issue, we i...
Aditya Dua, Benjamin Yolken, Nicholas Bambos