Design and Implementation of High-Performance Memory Systems for Future Packet Buffers

In this paper we address the design of a future high-speed router that supports line rates as high as OC-3072 (160 Gb/s), around one hundred ports and several service classes. Building such a high-speed router would raise many technological problems, one of them being the packet buffer design, mainly because in router design it is important to provide worst-case bandwidth guarantees and not just average-case optimizations. A previous packet buffer design provides worst-case bandwidth guarantees by using a hybrid SRAM/DRAM approach. Nextgeneration routers need to support hundreds of interfaces (i.e., ports and service classes). Unfortunately, high bandwidth for hundreds of interfaces requires the previous design to use large SRAMs which become a bandwidth bottleneck. The key observation we make is that the SRAM size is proportional to the DRAM access time but we can reduce the effective DRAM access time by overlapping multiple accesses to different banks, allowing us to reduce the SRAM...

• Type: Conference
• Year: 2003
• Where: MICRO
• Authors: Jorge García-Vidal, Jesús Corbal, Llorenç Cerdà, Mateo Valero
• Keywords: DRAM, Hardware, MICRO 2003, Packet Buffer Design, Worst-case Bandwidth Guarantees