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SAC
2010
ACM
13 years 9 months ago
An algorithm to generate the context-sensitive synchronized control flow graph
The verification of industrial systems specified with CSP often implies the analysis of many concurrent and synchronized components. The cost associated to these analyses is usu...
Marisa Llorens, Javier Oliver, Josep Silva, Salvad...
ISSS
1999
IEEE
151views Hardware» more  ISSS 1999»
13 years 8 months ago
Optimized System Synthesis of Complex RT Level Building Blocks from Multirate Dataflow Graphs
In order to cope with the ever increasing complexity of todays application specific integrated circuits, a building block based design methodology is established. The system is co...
Jens Horstmannshoff, Heinrich Meyr
SC
1990
ACM
13 years 8 months ago
Loop distribution with arbitrary control flow
Loop distribution is an integral part of transforming a sequential program into a parallel one. It is used extensively in parallelization,vectorization, and memory management. For...
Ken Kennedy, Kathryn S. McKinley
ARC
2010
Springer
167views Hardware» more  ARC 2010»
13 years 7 months ago
Systolic Algorithm Mapping for Coarse Grained Reconfigurable Array Architectures
Coarse Grained Reconfigurable Array (CGRA) architectures give high throughput and data reuse for regular algorithms while providing flexibility to execute multiple algorithms on th...
Kunjan Patel, Chris J. Bleakley
IFIP
1992
Springer
13 years 8 months ago
Controller Implementation by Communicating Asynchronous Sequential Circuits Generated from a Petri Net Specification of Required
This paper presents a completely systematic design procedure for asynchronous controllers. The initial step is the construction of a signal transition graph (STG, an interpreted P...
Jochen Beister, Ralf Wollowski