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ICPP
2002
IEEE
13 years 9 months ago
Optimal Code Size Reduction for Software-Pipelined Loops on DSP Applications
Code size expansion of software-pipelined loops is a critical problem for DSP systems with strict code size constraint. Some ad-hoc code size reduction techniques were used to try...
Qingfeng Zhuge, Zili Shao, Edwin Hsing-Mean Sha
DAC
2008
ACM
14 years 5 months ago
Enhancing timing-driven FPGA placement for pipelined netlists
FPGA application developers often attempt to use pipelining, Cslowing and retiming to improve the performance of their designs. Unfortunately, such registered netlists present a f...
Kenneth Eguro, Scott Hauck
IPPS
1998
IEEE
13 years 9 months ago
Register-Sensitive Software Pipelining
In this paper, we propose an integrated approach for register-sensitive software pipelining. In this approach, the heuristics proposed in the stage scheduling method of Eichenberg...
Amod K. Dani, V. Janaki Ramanan, Ramaswamy Govinda...
APVIS
2004
13 years 6 months ago
Inhomogeneous Force-Directed Layout Algorithms in the Visualisation Pipeline: From Layouts to Visualisations
The visualisation pipeline approach is a flexible and extensible technique for generating visualisations. The basic pipeline functions involve the capture and representation of da...
Neville Churcher, Warwick Irwin, Carl Cook
HPCC
2007
Springer
13 years 11 months ago
Software Pipelining for Packet Filters
Packet filters play an essential role in traffic management and security management on the Internet. In order to create software-based packet filters that are fast enough to work...
Yoshiyuki Yamashita, Masato Tsuru