93 search results - page 3 / 19 » An architectural level design methodology for embedded face ... |
CASES
2005
ACM
13 years 7 months ago
2005
ACM
This paper presents a methodology for monitoring security in Application Specific Instruction-set Processors (ASIPs). This is a generalized methodology for inline monitoring insec...
ICMCS
2006
IEEE
13 years 11 months ago
2006
IEEE
In this paper, a high-level optimization methodology is applied for the implementation of the well-known Convolutional Face Finder (CFF) algorithm for real-time applications on ce...
CODES
2005
IEEE
13 years 11 months ago
2005
IEEE
Majority of existing works on system level power estimation have focused on the processor, while there are very few that address power consumption of peripherals in a SoC. With th...
DATE
2008
IEEE
13 years 11 months ago
2008
IEEE
As levels of parallelism are becoming increasingly complex in multiprocessor architectures, GALS, and asynchronous circuits, methodologies and software tools are needed to verify ...
GLVLSI
2003
IEEE
13 years 10 months ago
2003
IEEE
In this paper, we address the problem of the efficient exploration of the architectural design space for parameterized systems. Since the design space is multi-objective, our aim ...