Sciweavers

178 search results - page 1 / 36
» An efficient approach for error diagnosis in HDL design
Sort
View
ISCAS
2003
IEEE
78views Hardware» more  ISCAS 2003»
13 years 10 months ago
An efficient approach for error diagnosis in HDL design
Che-Hua Shih, Jing-Yang Jou
ATS
2002
IEEE
95views Hardware» more  ATS 2002»
13 years 9 months ago
Effective Error Diagnosis for RTL Designs in HDLs
We propose an effective approach to diagnose multiple design errors in HDL designs with only one erroneous test case. Error candidates will be greatly reduced while ensuring that ...
Tai-Ying Jiang, Chien-Nan Jimmy Liu, Jing-Yang Jou
ATS
2003
IEEE
98views Hardware» more  ATS 2003»
13 years 10 months ago
Automatic Design Validation Framework for HDL Descriptions via RTL ATPG
We present a framework for high-level design validation using an efficient register-transfer level (RTL) automatic test pattern generator (ATPG). The RTL ATPG generates the test ...
Liang Zhang, Michael S. Hsiao, Indradeep Ghosh
DAC
2000
ACM
14 years 5 months ago
Self-test methodology for at-speed test of crosstalk in chip interconnects
The effect of crosstalk errors is most significant in highperformance circuits, mandating at-speed testing for crosstalk defects. This paper describes a self-test methodology that...
Xiaoliang Bai, Sujit Dey, Janusz Rajski
DAC
1994
ACM
13 years 9 months ago
Error Diagnosis for Transistor-Level Verification
This paper describes a diagnosis technique for locating design errors in circuit implementations which do not match their functional specification. The method efficiently propagat...
Andreas Kuehlmann, David Ihsin Cheng, Arvind Srini...