20 search results - page 3 / 4 » An efficient cache design for scalable glueless shared-memor... |
IPPS
2003
IEEE
13 years 10 months ago
2003
IEEE
Our recent work on uniprocessor and single-node multiprocessor (SMP) active memory systems uses address remapping techniques in conjunction with extended cache coherence protocols...
IPPS
2009
IEEE
13 years 12 months ago
2009
IEEE
Partitioned Global Address Space (PGAS) languages provide a unique programming model that can span shared-memory multiprocessor (SMP) architectures, distributed memory machines, o...
IEEEPACT
2008
IEEE
13 years 11 months ago
2008
IEEE
This paper presents the Distributed Cooperative Caching, a scalable and energy-efficient scheme to manage chip multiprocessor (CMP) cache resources. The proposed configuration is...
ISCA
2000
IEEE
13 years 9 months ago
2000
IEEE
The microprocessor industry is currently struggling with higher development costs and longer design times that arise from exceedingly complex processors that are pushing the limit...
ISCA
1998
IEEE
13 years 9 months ago
1998
IEEE
Alewife is a multiprocessor architecture that supports up to 512 processing nodes connected over a scalable and cost-effective mesh network at a constant cost per node. The MIT Al...