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» An exact algorithm for wirelength optimal placements in VLSI...
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DAC
2000
ACM
14 years 7 months ago
Can recursive bisection alone produce routable placements?
This work focuses on congestion-driven placement of standard cells into rows in the fixed-die context. We summarize the stateof-the-art after two decades of research in recursive ...
Andrew E. Caldwell, Andrew B. Kahng, Igor L. Marko...
ISPD
2007
ACM
128views Hardware» more  ISPD 2007»
13 years 7 months ago
X-architecture placement based on effective wire models
In this paper, we derive the X-half-perimeter wirelength (XHPWL) model for X-architecture placement and explore the effects of three different wire models on X-architecture plac...
Tung-Chieh Chen, Yi-Lin Chuang, Yao-Wen Chang
ASPDAC
2000
ACM
159views Hardware» more  ASPDAC 2000»
13 years 10 months ago
Analytical minimization of half-perimeter wirelength
Global placement of hypergraphs is critical in the top-down placement of large timing-driven designs 10, 16 . Placement quality is evaluated in terms of the half-perimeter wirelen...
Andrew A. Kennings, Igor L. Markov
GECCO
2005
Springer
148views Optimization» more  GECCO 2005»
13 years 11 months ago
Multiobjective VLSI cell placement using distributed genetic algorithm
Genetic Algorithms have worked fairly well for the VLSI cell placement problem, albeit with significant run times. Two parallel models for GA are presented for VLSI cell placemen...
Sadiq M. Sait, Mohammed Faheemuddin, Mahmood R. Mi...
ISCAS
2005
IEEE
133views Hardware» more  ISCAS 2005»
13 years 11 months ago
Multiobjective VLSI cell placement using distributed simulated evolution algorithm
— Simulated Evolution (SimE) is a sound stochastic approximation algorithm based on the principles of adaptation. If properly engineered it is possible for SimE to reach nearopti...
Sadiq M. Sait, Ali Mustafa Zaidi, Mustafa I. Ali