8 search results - page 1 / 2 » An experimental evaluation of tiling and shackling for memor... |
ICS
1999
Tsinghua U.
13 years 9 months ago
1999
Tsinghua U.
On modern computers, the performance of programs is often limited by memory latency rather than by processor cycle time. To reduce the impact of memory latency, the restructuring ...
DSD
2004
IEEE
13 years 8 months ago
2004
IEEE
Tile-based rendering (also called chunk rendering or bucket rendering) is a promising technique for low-power, 3D graphics platforms. This technique decomposes a scene into smalle...
ISCA
2007
IEEE
13 years 11 months ago
2007
IEEE
Server consolidation is becoming an increasingly popular technique to manage and utilize systems. This paper develops CMP memory systems for server consolidation where most sharin...
PLDI
2010
ACM
13 years 10 months ago
2010
ACM
This paper presents a novel optimizing compiler for general purpose computation on graphics processing units (GPGPU). It addresses two major challenges of developing high performa...
EUROPAR
2010
Springer
13 years 6 months ago
2010
Springer
Abstract. Traditional parallel programming methodologies for improving performance assume cache-based parallel systems. However, new architectures, like the IBM Cyclops-64 (C64), b...