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ISVLSI
2003
IEEE
97views VLSI» more  ISVLSI 2003»
13 years 10 months ago
Q-Tree: A New Iterative Improvement Approach for Buffered Interconnect Optimization
The “chicken-egg” dilemma between VLSI interconnect timing optimization and delay calculation suggests an iterative approach. We separate interconnect timing transformation as...
Andrew B. Kahng, Bao Liu
ICCS
2005
Springer
13 years 10 months ago
Improved Tag Set Design and Multiplexing Algorithms for Universal Arrays
In this paper we address two optimization problems arising in the design of genomic assays based on universal tag arrays. First, we address the universal array tag set design probl...
Ion I. Mandoiu, Claudia Prajescu, Dragos Trinca
ICCAD
2010
IEEE
229views Hardware» more  ICCAD 2010»
13 years 3 months ago
Obstacle-avoiding rectilinear Steiner minimum tree construction: An optimal approach
In this paper, we present an efficient method to solve the obstacle-avoiding rectilinear Steiner minimum tree (OARSMT) problem optimally. Our work is a major improvement over the w...
Tao Huang, Evangeline F. Y. Young
GECCO
2004
Springer
103views Optimization» more  GECCO 2004»
13 years 10 months ago
Using a Genetic Algorithm to Design and Improve Storage Area Network Architectures
Abstract. Designing storage area networks is an NP-hard problem. Previous work has focused on traditional algorithmic techniques to automatically determine fabric requirements, net...
Elizabeth Dicke, Andrew Byde, Paul J. Layzell, Dav...
NI
2011
168views more  NI 2011»
12 years 8 months ago
Automated Reconstruction of Dendritic and Axonal Trees by Global Optimization with Geometric Priors
We present a novel probabilistic approach to fully automated delineation of tree structures in noisy 2D images and 3D image stacks. Unlike earlier methods that rely mostly on local...
Engin Türetken, Germán González...