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» An improvement in formal verification
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FORTE
1994
13 years 6 months ago
An improvement in formal verification
Critical safety and liveness properties of a concurrent system can often be proven with the help of a reachability analysis of a finite state model. This type of analysis is usual...
Gerard J. Holzmann, Doron Peled
ENTCS
2006
125views more  ENTCS 2006»
13 years 5 months ago
Parallel Assignments in Software Model Checking
In this paper we investigate how formal software verification systems can be improved by utilising parallel assignment in weakest precondition computations.
Murray Stokely, Sagar Chaki, Joël Ouaknine
JISE
1998
106views more  JISE 1998»
13 years 4 months ago
Control / Data-Flow Analysis for VHDL Semantic Extraction
straction reduces the number of states necessary to perform formal verification while maintaining the functionality of the original model with respect to ifications to be verified....
Yee-Wing Hsieh, Steven P. Levitan
DAC
2001
ACM
14 years 6 months ago
Formal Property Verification by Abstraction Refinement with Formal, Simulation and Hybrid Engines
roperty Verification by Abstraction Refinement with Formal, Simulation and Hybrid Engines Dong Wang , Pei-Hsin Ho , Jiang Long , James Kukula Yunshan Zhu , Tony Ma , Robert D...
Dong Wang, Pei-Hsin Ho, Jiang Long, James H. Kukul...
CAV
2010
Springer
286views Hardware» more  CAV 2010»
13 years 5 months ago
ABC: An Academic Industrial-Strength Verification Tool
ABC is a public-domain system for logic synthesis and formal verification of binary logic circuits appearing in synchronous hardware designs. ABC combines scalable logic transforma...
Robert K. Brayton, Alan Mishchenko