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ICCAD
1999
IEEE
72views Hardware» more  ICCAD 1999»
13 years 9 months ago
An integrated algorithm for combined placement and libraryless technology mapping
This paper presents a new solution for combining technology mapping with placement, coupling the two into one phase. The original aspects of our work are the use of libraryless ma...
Yanbin Jiang, Sachin S. Sapatnekar
ASPDAC
1998
ACM
101views Hardware» more  ASPDAC 1998»
13 years 9 months ago
An Integrated Flow for Technology Remapping and Placement of Sub-half-micron Circuits
ABSTRACT - This paper presents a new design flow, FPDSiMPA, and a set of techniques for synthesizing high-performance sub-half micron logic circuits. FPD-SiMPA consists of logic p...
Jinan Lou, Amir H. Salek, Massoud Pedram
FPGA
2009
ACM
209views FPGA» more  FPGA 2009»
13 years 11 months ago
SPR: an architecture-adaptive CGRA mapping tool
In this paper we present SPR, a new architecture-adaptive mapping tool for use with Coarse-Grained Reconfigurable Architectures (CGRAs). It combines a VLIW style scheduler and FP...
Stephen Friedman, Allan Carroll, Brian Van Essen, ...
DAC
2006
ACM
14 years 6 months ago
Optimal simultaneous mapping and clustering for FPGA delay optimization
Both technology mapping and circuit clustering have a large impact on FPGA designs in terms of circuit performance, area, and power dissipation. Existing FPGA design flows carry o...
Joey Y. Lin, Deming Chen, Jason Cong
ICCAD
2002
IEEE
110views Hardware» more  ICCAD 2002»
14 years 1 months ago
Whirlpool PLAs: a regular logic structure and their synthesis
 A regular circuit structure called a Whirlpool PLA (WPLA) is proposed. It is suitable for the implementation of finite state machines as well as combinational logic. A WPLA is ...
Fan Mo, Robert K. Brayton