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ECBS
2006
IEEE
153views Hardware» more  ECBS 2006»
13 years 9 months ago
A Unified Approach for Verification and Validation of Systems and Software Engineering Models
We present in this paper a unified paradigm for the verification and validation of software and systems engineering design models expressed in UML 2.0 or SysML. This paradigm reli...
Luay Alawneh, Mourad Debbabi, Yosr Jarraya, Andrei...
EURODAC
1994
IEEE
211views VHDL» more  EURODAC 1994»
13 years 10 months ago
Advanced simulation and modeling techniques for hardware quality verification of digital systems
synchronisation also play a fundamental role in overall system robustness. ElectroMagnetic Compatibility (EMC) and ElectroMagnetic Interference (EMI) issues also have to be conside...
S. Forno, Stephen Rochel
ISSS
2002
IEEE
127views Hardware» more  ISSS 2002»
13 years 10 months ago
Validation in a Component-Based Design Flow for Multicore SoCs
Currently, since many SoCs include heterogeneous components such as CPUs, DSPs, ASICs, memories, buses, etc., system integration becomes a major step in the design flow. To enable...
Ahmed Amine Jerraya, Sungjoo Yoo, Aimen Bouchhima,...
DATE
2006
IEEE
112views Hardware» more  DATE 2006»
13 years 11 months ago
On the verification of automotive protocols
Verification quality is a must for functional safety in electronic systems. In automotive, the verification flow is historically based on a layered approach, where each level (mod...
G. Zarri, F. Colucci, F. Dupuis, R. Mariani, M. Pa...
DSD
2005
IEEE
116views Hardware» more  DSD 2005»
13 years 11 months ago
Validation of Embedded Systems Using Formal Method Aided Simulation
This paper proposes a validation approach, based on simulation, which addresses problems related to both state space explosion of formal methods and low coverage of informal metho...
Daniel Karlsson, Petru Eles, Zebo Peng