67 search results - page 1 / 14 » An integrated floorplanning with an efficient buffer plannin... |
ISPD
2003
ACM
13 years 10 months ago
2003
ACM
Previous works on buffer planning are mainly based on fixed die placement. It is necessary to reduce the complexity of computing the feasible buffer insertion sites to integrate t...
ISQED
2009
IEEE
13 years 11 months ago
2009
IEEE
As technology advances, the interconnect delay among modules plays dominant role in chip performance. Buffer insertion, as a traditional approach to reduce wire delay in 2D ICs, i...
ICCAD
1999
IEEE
13 years 9 months ago
1999
IEEE
This paper studies buffer block planning for interconnect-driven floorplanning in deep submicron designs. We first introduce the concept of feasible region (FR) for buffer inserti...
ISCAS
2003
IEEE
13 years 10 months ago
2003
IEEE
In this paper, we introduce a tile-graph-based approach to power planning. For a given flooplan solution, the power inputs are modeled into a tile graph, the minimum capacity of e...
ICCAD
2004
IEEE
14 years 1 months ago
2004
IEEE
As the technology progresses, interconnect delays have become bottlenecks of chip performance. Three dimensional (3D) integrated circuits are proposed as one way to address this p...