67 search results - page 2 / 14 » An integrated floorplanning with an efficient buffer plannin... |
ASPDAC
2004
ACM
13 years 10 months ago
2004
ACM
As the process technology advances into the deep submicron era, interconnect plays a dominant role in determining circuit performance and signal integrity. Buffer insertion is one...
ASPDAC
2008
ACM
13 years 7 months ago
2008
ACM
It's a trend to consider power supply integrity at early stage to improve the design quality. In this paper, we propose a novel algorithm to optimize floorplan together with P...
ASPDAC
2001
ACM
13 years 9 months ago
2001
ACM
One of the most challenging issues in today's high-performance VLSI design is to ensure high-quality power supply to each individual circuit blocks. Reduced power supply volt...
VLSID
2002
IEEE
14 years 5 months ago
2002
IEEE
We describe a new algorithm for floorplan evaluation using timing-driven buffered routing according to a prescribed buffer site map. Specifically, we describe a provably good mult...
DAC
2008
ACM
14 years 6 months ago
2008
ACM
In this paper, we present DeFer -- a fast, high-quality and nonstochastic fixed-outline floorplanning algorithm. DeFer generates a non-slicing floorplan by compacting a slicing fl...