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» An iterative logarithmic multiplier
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MAM
2011
349views Communications» more  MAM 2011»
12 years 12 months ago
An iterative logarithmic multiplier
The paper presents a new multiplier enabling achievement of an arbitrary accuracy. It follows the same idea of number representation as the Mitchell’s algorithm, but does not use...
Zdenka Babic, Aleksej Avramovic, Patricio Bulic
VLSID
2006
IEEE
240views VLSI» more  VLSID 2006»
14 years 5 months ago
An Efficient and Accurate Logarithmic Multiplier Based on Operand Decomposition
Logarithmic Number Systems (LNS) offer a viable alternative in terms of area, delay and power to binary number systems for multiplication and division operations in signal process...
Venkataraman Mahalingam, N. Ranganathan
ASYNC
2004
IEEE
133views Hardware» more  ASYNC 2004»
13 years 8 months ago
An Asynchronous, Iterative Implementation of the Original Booth Multiplication Algorithm
One of the main reasons for using asynchronous design is that it offers the opportunity to exploit the datadependent latency of many operations in order to achieve low-power, high...
Aristides Efthymiou, W. Suntiamorntut, Jim D. Gars...
ICCD
2004
IEEE
154views Hardware» more  ICCD 2004»
14 years 1 months ago
A High-Frequency Decimal Multiplier
Decimal arithmetic is regaining popularity in the computing community due to the growing importance of commercial, financial, and Internet-based applications, which process decima...
Robert D. Kenney, Michael J. Schulte, Mark A. Erle
ICCD
2001
IEEE
144views Hardware» more  ICCD 2001»
14 years 1 months ago
An Area-Efficient Iterative Modified-Booth Multiplier Based on Self-Timed Clocking
A new iterative multiplier based on a self-timed clocking scheme is presented. To reduce the area required for the multiplier, only two CSA rows are iteratively used to complete a...
Myoung-Cheol Shin, Se-Hyeon Kang, In-Cheol Park