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» An on Chip ADC Test Structure
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DATE
2006
IEEE
126views Hardware» more  DATE 2006»
13 years 11 months ago
Analysis and modeling of power grid transmission lines
Power distribution and signal transmission are becoming key limiters for chip performance in nanometer era. These issues can be simultaneously addressed by designing transmission ...
J. Balachandran, Steven Brebels, G. Carchon, T. We...
IJSNET
2008
113views more  IJSNET 2008»
13 years 5 months ago
Reservation-based protocol for monitoring applications using IEEE 802.15.4 sensor networks
: The IEEE 802.15.4 and Zigbee are protocols aimed at low-duty and low-power wireless sensor networks. Continuously monitoring applications such as applications of structural healt...
Vidya Krishnamurthy, Edward Sazonov
IOLTS
2008
IEEE
102views Hardware» more  IOLTS 2008»
14 years 1 days ago
Integrating Scan Design and Soft Error Correction in Low-Power Applications
— Error correcting coding is the dominant technique to achieve acceptable soft-error rates in memory arrays. In many modern circuits, the number of memory elements in the random ...
Michael E. Imhof, Hans-Joachim Wunderlich, Christi...
CIS
2005
Springer
13 years 11 months ago
Moving Block Sequence and Organizational Evolutionary Algorithm for General Floorplanning
⎯A new nonslicing floorplan representation, the moving block sequence (MBS), is proposed in this paper. Our idea of the MBS originates from the observation that placing blocks on...
Jing Liu, Weicai Zhong, Licheng Jiao
ISCA
2008
IEEE
132views Hardware» more  ISCA 2008»
14 years 1 days ago
Online Estimation of Architectural Vulnerability Factor for Soft Errors
As CMOS technology scales and more transistors are packed on to the same chip, soft error reliability has become an increasingly important design issue for processors. Prior resea...
Xiaodong Li, Sarita V. Adve, Pradip Bose, Jude A. ...