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» An on Chip ADC Test Structure
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DAC
2002
ACM
14 years 6 months ago
DRG-cache: a data retention gated-ground cache for low power
In this paper we propose a novel integrated circuit and architectural level technique to reduce leakage power consumption in high performance cache memories using single Vt (trans...
Amit Agarwal, Hai Li, Kaushik Roy
MICRO
2009
IEEE
124views Hardware» more  MICRO 2009»
13 years 12 months ago
ZerehCache: armoring cache architectures in high defect density technologies
Aggressive technology scaling to 45nm and below introduces serious reliability challenges to the design of microprocessors. Large SRAM structures used for caches are particularly ...
Amin Ansari, Shantanu Gupta, Shuguang Feng, Scott ...
ASPLOS
2010
ACM
14 years 1 days ago
Virtualized and flexible ECC for main memory
We present a general scheme for virtualizing main memory errorcorrection mechanisms, which map redundant information needed to correct errors into the memory namespace itself. We ...
Doe Hyun Yoon, Mattan Erez
ASPDAC
1995
ACM
103views Hardware» more  ASPDAC 1995»
13 years 8 months ago
A scheduling algorithm for multiport memory minimization in datapath synthesis
- In this paper, we present a new scheduling algorithms that generates area-efficient register transfer level datapaths with multiport memories. The proposed scheduling algorithm a...
Hae-Dong Lee, Sun-Young Hwang
BMCBI
2007
200views more  BMCBI 2007»
13 years 5 months ago
Assessment of algorithms for high throughput detection of genomic copy number variation in oligonucleotide microarray data
Background: Genomic deletions and duplications are important in the pathogenesis of diseases, such as cancer and mental retardation, and have recently been shown to occur frequent...
Ágnes Baross, Allen D. Delaney, H. Irene Li...