ZerehCache: armoring cache architectures in high defect density technologies

Aggressive technology scaling to 45nm and below introduces serious reliability challenges to the design of microprocessors. Large SRAM structures used for caches are particularly sensitive to process variation due to their high density and organization. Designers typically over-provision caches with additional resources to overcome the hard-faults. However, static allocation and binding of redundant resources results in low utilization of the extra resources and ultimately limits the number of defects that can be tolerated. This work re-examines the design of process variation tolerant onchip caches with the focus on flexibility and dynamic reconfigurability to allow a large number defects to be tolerated with modest hardware overhead. Our approach, ZerehCache, combines redundant data array elements with a permutation network for providing a higher degree of freedom on replacement. A graph coloring algorithm is used to configure the network and find the proper mapping of replaceme...

• Type: Conference
• Year: 2009
• Where: MICRO
• Authors: Amin Ansari, Shantanu Gupta, Shuguang Feng, Scott A. Mahlke
• Keywords: Hardware, MICRO 2009, Over-provision Caches, Process Variation, Tolerant Onchip Caches