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    IPPS
    2006
    IEEE
    124views Distributed And Parallel Com...» more  IPPS 2006»
    An optimal architecture for a DDC
    13 years 11 months ago
    An optimal architecture for a DDC
    Download  eprints.eemcs.utwente.nl
    Digital Down Conversion (DDC) is an algorithm, used to lower the amount of samples per second by selecting a limited frequency band out of a stream of samples. A possible DDC algo...
    Tjerk Bijlsma, Pascal T. Wolkotte, Gerard J. M. Sm...
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    DAC
    1997
    ACM
    77views Computer Architecture» more  DAC 1997»
    Timing Optimization for Multi-Source Nets: Characterization and Optimal Repeater Insertion
    13 years 9 months ago
    Timing Optimization for Multi-Source Nets: Characterization and Optimal Repeater Insertion
    Download  www.cs.uic.edu
    John Lillis, Chung-Kuan Cheng
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    DAC
    1997
    ACM
    98views Computer Architecture» more  DAC 1997»
    High-Level Power Modeling, Estimation, and Optimization
    13 years 9 months ago
    High-Level Power Modeling, Estimation, and Optimization
    Download  atrak.usc.edu
    Enrico Macii, Massoud Pedram, Fabio Somenzi
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    DAC
    1996
    ACM
    92views Computer Architecture» more  DAC 1996»
    Concurrent Analysis Techniques for Data Path Timing Optimization
    13 years 9 months ago
    Concurrent Analysis Techniques for Data Path Timing Optimization
    Download  bears.ece.ucsb.edu
    Chuck Monahan, Forrest Brewer
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    DAC
    1996
    ACM
    84views Computer Architecture» more  DAC 1996»
    Optimal Clock Period FPGA Technology Mapping for Sequential Circuits
    13 years 9 months ago
    Optimal Clock Period FPGA Technology Mapping for Sequential Circuits
    Download  www.eecs.berkeley.edu
    Peichen Pan, C. L. Liu
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