Sciweavers

32 search results - page 1 / 7
» Analysis of SEU Effects in a Pipelined Processor
Sort
View
IOLTS
2002
IEEE
115views Hardware» more  IOLTS 2002»
13 years 10 months ago
Analysis of SEU Effects in a Pipelined Processor
Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo ...
CSREAESA
2009
13 years 6 months ago
Embedded Processor Based Fault Injection and SEU Emulation for FPGAs
Two embedded processor based fault injection case studies are presented which are applicable to Field Programmable Gate Arrays (FPGAs) and FPGA cores in configurable System-on-Chip...
Bradley F. Dutton, Mustafa Ali, Charles E. Stroud,...
RTSS
2008
IEEE
13 years 11 months ago
Merging State and Preserving Timing Anomalies in Pipelines of High-End Processors
Many embedded systems are subject to temporal constraints that require advance guarantees on meeting deadlines. Such systems rely on static analysis to safely bound worst-case exe...
Sibin Mohan, Frank Mueller
RTS
2006
129views more  RTS 2006»
13 years 5 months ago
Modeling out-of-order processors for WCET analysis
Estimating the Worst Case Execution Time (WCET) of a program on a given processor is important for the schedulability analysis of real-time systems. WCET analysis techniques typic...
Xianfeng Li, Abhik Roychoudhury, Tulika Mitra
DATE
2006
IEEE
115views Hardware» more  DATE 2006»
13 years 11 months ago
Optimal periodic testing of intermittent faults in embedded pipelined processor applications
Today’s nanometer technology trends have a very negative impact on the reliability of semiconductor products. Intermittent faults constitute the largest part of reliability fail...
Nektarios Kranitis, Andreas Merentitis, N. Laoutar...