18 search results - page 2 / 4 » Analysis of The Test Data Volume Reduction Benefit of Modula... |
ITC
1998
IEEE
13 years 9 months ago
1998
IEEE
This paper explores defects found in a high volume microprocessor when shipping at a low defect level. A brief description of the manufacturing flow along with definition of DPM i...
ITC
2003
IEEE
13 years 10 months ago
2003
IEEE
This paper discusses the adoption of Embedded Deterministic Test (EDT) at Infineon Technologies as a means to reduce the cost of manufacturing test without compromising test quali...
DAC
2003
ACM
13 years 10 months ago
2003
ACM
We propose in this paper an extension on the Scan Chain Concealment technique to further reduce test time and volume requirement. The proposed methodology stems from the architect...
VTS
2003
IEEE
13 years 10 months ago
2003
IEEE
In this paper, an efficient technique for test data volume reduction based on the shared scan-in (Illinois Scan) architecture and the scan chain reconfiguration (Dynamic Scan) arc...
ITC
2003
IEEE
13 years 10 months ago
2003
IEEE
This paper presents an approach for reducing the test data volume that has to be stored in ATE vector memory for IC manufacturing testing. We exploit the capabilities of present A...