111 search results - page 1 / 23 » Analysis of power consumption in VLSI global interconnects |
ISCAS
2005
IEEE
13 years 10 months ago
2005
IEEE
Abstract— The analysis of effects induced by interconnects become increasingly important as the scale of process technologies steadily shrinks. While most analyses focus on the t...
IOLTS
2003
IEEE
13 years 10 months ago
2003
IEEE
On-chip global interconnections in very deep submicron technology (VDSM) ICs are becoming more sensitive and prone to errors caused by power supply noise, crosstalk noise, delay v...
HPCA
2005
IEEE
13 years 10 months ago
2005
IEEE
Future high-performance billion-transistor processors are likely to employ partitioned architectures to achieve high clock speeds, high parallelism, low design complexity, and low...
ICCAD
2005
IEEE
14 years 1 months ago
2005
IEEE
The work in this paper analyses the applicability of carbon nanotube (CNT) bundles as interconnects for VLSI circuits, while taking into account the practical limitations in this ...
ISLPED
2007
ACM
13 years 6 months ago
2007
ACM
This paper addresses the problem of power-optimal repeater insertion for global buses in the presence of crosstalk noise. MTCMOS technique by inserting high-Vth sleep transistors ...