6 search results - page 1 / 2 » Analysis of timing jitter in ring oscillators due to power s... |
ISCAS
2003
IEEE
13 years 10 months ago
2003
IEEE
∑= += N i firiT 1 0 )( ττ (1) This paper presents a time-domain method for estimating the jitter in ring oscillators that is due to power supply noise. The method is used to a...
ICCD
2001
IEEE
14 years 2 months ago
2001
IEEE
CMOS Phase-locked loops (PLL) are ubiquitous in RF and mixed-signal integrated circuits. PLLs are very sensitive to noise fluctuations on the power and ground rails. In this paper...
PATMOS
2005
Springer
13 years 10 months ago
2005
Springer
Abstract. Based on a previously reported request driven technique for Globally-Asynchronous Locally-Synchronous (GALS) circuits this paper presents two significant enhancements. Fi...
DAC
2007
ACM
14 years 6 months ago
2007
ACM
Due to shrinking technology, increasing functional frequency and density, and reduced noise margins with supply voltage scaling, the sensitivity of designs to supply voltage noise...
MICRO
2006
IEEE
13 years 11 months ago
2006
IEEE
Power delivery is a growing reliability concern in microprocessors as the industry moves toward feature-rich, powerhungrier designs. To battle the ever-aggravating power consumpti...