534 search results - page 1 / 107 » Analytical router modeling for networks-on-chip performance ... |
AINA
2009
IEEE
13 years 11 months ago
2009
IEEE
This paper presents a novel analytical model to compute communication latency of broadcast as the most fundamental collective communication operation. The novelty of the model lie...
DATE
2007
IEEE
13 years 11 months ago
2007
IEEE
Networks-on-Chip (NoCs) have recently emerged as a scalable alternative to classical bus and point-to-point architectures. To date, performance evaluation of NoC designs is largel...
ICCAD
2009
IEEE
13 years 2 months ago
2009
IEEE
Performance models for Network-on-Chip (NoC) are essential for design, optimization and Quality of Service (QoS) assurance. Classical queueing theory has been often used to provid...
ASPDAC
2010
ACM
13 years 2 months ago
2010
ACM
Over the course of this decade, uniprocessor chips have given way to multi-core chips which have become the primary building blocks of today's computer systems. The presence o...
ISCAS
2006
IEEE
13 years 10 months ago
2006
IEEE
— This paper analyzes the behavior of interconnects in the highly structured environment of a network-on-chip (NoC). Two distinct classes of wires are considered, namely links be...