23 search results - page 1 / 5 » Analyzing timing uncertainty in mesh-based clock architectur... |
DATE
2006
IEEE
13 years 11 months ago
2006
IEEE
Mesh architectures are used to distribute critical global signals on a chip, such as clock and power/ground. Redundancy created by mesh loops smooths out undesirable variations be...
DAC
2007
ACM
13 years 9 months ago
2007
ACM
With the continuous increase of circuit density, interconnect length, and aspect ratio, the influence of capacitive and inductive coupling on timing characteristics of integrated ...
SENSYS
2005
ACM
13 years 10 months ago
2005
ACM
Radio duty cycling has received significant attention in sensor networking literature, particularly in the form of protocols for medium access control and topology management. Whi...
ECOOP
1993
Springer
13 years 9 months ago
1993
Springer
This paper proposes a formalism for reasoning about distributed object-oriented computations. The formalism is an extension of Milner’s CCS with the notion of local time. It allo...
VLSID
2005
IEEE
14 years 5 months ago
2005
IEEE
Timing margin (slack) needs to be carefully managed to ensure a satisfactory timing yield. We propose a new design flow that combines a false-path-aware gate sizing and a statisti...