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» Application of Internode Model to Global Power Consumption E...
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SLIP
2009
ACM
13 years 11 months ago
Floorplan-based FPGA interconnect power estimation in DSP circuits
A novel high-level approach for estimating power consumption of global interconnects in data-path oriented designs implemented in FPGAs is presented. The methodology is applied to...
Ruzica Jevtic, Carlos Carreras, Vukasin Pejovic
ICCAD
2005
IEEE
147views Hardware» more  ICCAD 2005»
14 years 1 months ago
NoCEE: energy macro-model extraction methodology for network on chip routers
In this paper we present NoCEE, a fast and accurate method for extracting energy models for packet-switched Network on Chip (NoC) routers. Linear regression is used to model the r...
Jeremy Chan, Sri Parameswaran
ICCD
2006
IEEE
117views Hardware» more  ICCD 2006»
14 years 1 months ago
System-Level Energy Modeling for Heterogeneous Reconfigurable Chip Multiprocessors
—Field-Programmable Gate Array (FPGA) technology is characterized by continuous improvements that provide new opportunities in system design. Multiprocessors-ona-Programmable-Chi...
Xiaofang Wang, Sotirios G. Ziavras
DATE
2005
IEEE
118views Hardware» more  DATE 2005»
13 years 10 months ago
An Iterative Algorithm for Battery-Aware Task Scheduling on Portable Computing Platforms
In this work we consider battery powered portable systems which either have Field Programmable Gate Arrays (FPGA) or voltage and frequency scalable processors as their main proces...
Jawad Khan, Ranga Vemuri