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HPCA
2009
IEEE
14 years 6 months ago
Dynamic hardware-assisted software-controlled page placement to manage capacity allocation and sharing within large caches
In future multi-cores, large amounts of delay and power will be spent accessing data in large L2/L3 caches. It has been recently shown that OS-based page coloring allows a non-uni...
Manu Awasthi, Kshitij Sudan, Rajeev Balasubramonia...
ICPP
2008
IEEE
13 years 12 months ago
Taming Single-Thread Program Performance on Many Distributed On-Chip L2 Caches
This paper presents a two-part study on managing distributed NUCA (Non-Uniform Cache Architecture) L2 caches in a future manycore processor to obtain high singlethread program per...
Lei Jin, Sangyeun Cho
IPPS
1999
IEEE
13 years 9 months ago
Cashmere-VLM: Remote Memory Paging for Software Distributed Shared Memory
Software distributed shared memory (DSM) systems have successfully provided the illusion of shared memory on distributed memory machines. However, most software DSM systems use th...
Sandhya Dwarkadas, Robert Stets, Nikos Hardavellas...
IEEEPACT
2009
IEEE
14 years 2 days ago
SOS: A Software-Oriented Distributed Shared Cache Management Approach for Chip Multiprocessors
Abstract—This paper proposes a new software-oriented approach for managing the distributed shared L2 caches of a chip multiprocessor (CMP) for latency-oriented multithreaded appl...
Lei Jin, Sangyeun Cho
ASPLOS
2012
ACM
12 years 1 months ago
Scalable address spaces using RCU balanced trees
Software developers commonly exploit multicore processors by building multithreaded software in which all threads of an application share a single address space. This shared addre...
Austin T. Clements, M. Frans Kaashoek, Nickolai Ze...