The phase-ordering problem is a long standing issue for compiler writers. Most optimizing compilers typically have numerous different code-improving phases, many of which can be a...
Prasad Kulkarni, David B. Whalley, Gary S. Tyson, ...
Transaction-level modeling has been touted to improve simulation performance and modeling efficiency for early design space exploration. But no tools are available to generate suc...
Dongwan Shin, Andreas Gerstlauer, Junyu Peng, Rain...
In this paper, we are concerned about the performance estimation of bus-based architectures assuming that the task partitioning on the processing components is already determined....
This paper presents a methodology to combine Transaction Level Modeling and System/Network co-simulation for the design of networked embedded systems. As a result, a new design di...
Multi-million gate System-on-Chip (SoC) designs increasingly rely on Intellectual Property (IP) blocks. However, due to technology scaling the leakage power consumption of the IP ...
Aseem Gupta, Nikil D. Dutt, Fadi J. Kurdahi, Kamal...