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2003
IEEE

Schedule-aware performance estimation of communication architecture for efficient design space exploration

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Schedule-aware performance estimation of communication architecture for efficient design space exploration
In this paper, we are concerned about the performance estimation of bus-based architectures assuming that the task partitioning on the processing components is already determined. Since the communication behavior is usually unpredictable due to dynamic bus requests of processing components, bus contention, and so on, simulation based approach seems inevitable for accurate performance estimation. But it is too time consuming to explore the wide design space. To overcome this serious drawback, we propose a static performance estimation method that is based on the queuing model and makes use of memory traces and task execution schedule information. We propose to use this static estimation approach to prune the design space drastically before applying a simulation-based approach. Comparison with tracedriven simulation results proves the validity of our static estimation technique. Categories and Subject Descriptors B.8.2 [Hardware]: Performance and Reliability – Performance Analysis and...
Sungchan Kim, Chaeseok Im, Soonhoi Ha
Added 04 Jul 2010
Updated 04 Jul 2010
Type Conference
Year 2003
Where CODES
Authors Sungchan Kim, Chaeseok Im, Soonhoi Ha
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