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CODES
2003
IEEE
13 years 11 months ago
A modular simulation framework for architectural exploration of on-chip interconnection networks
Ever increasing complexity and heterogeneity of SoC platforms require diversified on-chip communication schemes beyond the currently omnipresent shared bus architectures. To prev...
Tim Kogel, Malte Doerper, Andreas Wieferink, Raine...
BWCCA
2010
13 years 18 days ago
Advanced Design Issues for OASIS Network-on-Chip Architecture
Network-on-Chip (NoC) architectures provide a good way of realizing efficient interconnections and largely alleviate the limitations of bus-based solutions. NoC has emerged as a so...
Kenichi Mori, Adam Esch, Abderazek Ben Abdallah, K...
ISCA
2009
IEEE
186views Hardware» more  ISCA 2009»
14 years 6 days ago
Application-aware deadlock-free oblivious routing
Conventional oblivious routing algorithms are either not application-aware or assume that each flow has its own private channel to ensure deadlock avoidance. We present a framewo...
Michel A. Kinsy, Myong Hyon Cho, Tina Wen, G. Edwa...