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» Approximating Low Latency Queueing Buffer Latency
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ISCA
2005
IEEE
144views Hardware» more  ISCA 2005»
13 years 10 months ago
Scalable Load and Store Processing in Latency Tolerant Processors
Memory latency tolerant architectures support thousands of in-flight instructions without scaling cyclecritical processor resources, and thousands of useful instructions can compl...
Amit Gandhi, Haitham Akkary, Ravi Rajwar, Srikanth...
TCAD
2008
103views more  TCAD 2008»
13 years 4 months ago
Topology-Based Performance Analysis and Optimization of Latency-Insensitive Systems
Latency-insensitive protocols allow system-on-chip (SoC) engineers to decouple the design of the computing cores from the design of the intercore communication channels while follo...
Rebecca L. Collins, Luca P. Carloni
INFOCOM
1998
IEEE
13 years 9 months ago
Implementing Distributed Packet Fair Queueing in a Scalable Switch Architecture
To support the Internet's explosive growth and expansion into a true integrated services network, there is a need for cost-effective switching technologies that can simultaneo...
Donpaul C. Stephens, Hui Zhang
INFOCOM
1996
IEEE
13 years 9 months ago
Latency-Rate Servers: A General Model for Analysis of Traffic Scheduling Algorithms
In this paper, we develop a general model, called Latency-Rate servers (LR servers), for the analysis of traffic scheduling algorithms in broadband packet networks. The behavior of...
Dimitrios Stiliadis, Anujan Varma
ARITH
2005
IEEE
13 years 10 months ago
Low Latency Pipelined Circular CORDIC
The pipelined CORDIC with linear approximation to rotation has been proposed to achieve reductions in delay, power and area; however, the schemes for rotation (multiplication) and...
Elisardo Antelo, Julio Villalba