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» Arbitrary Error Detection in Combinational Circuits by Using...
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ITC
2000
IEEE
101views Hardware» more  ITC 2000»
13 years 10 months ago
Which concurrent error detection scheme to choose ?
Concurrent error detection (CED) techniques (based on hardware duplication, parity codes, etc.) are widely used to enhance system dependability. All CED techniques introduce some ...
Subhasish Mitra, Edward J. McCluskey
TVLSI
2008
107views more  TVLSI 2008»
13 years 5 months ago
Novel Probabilistic Combinational Equivalence Checking
Exact approaches to combinational equivalence checking, such as automatic test pattern generation-based, binary decision diagrams (BDD)-based, satisfiability-based, and hybrid appr...
Shih-Chieh Wu, Chun-Yao Wang, Yung-Chih Chen
DSD
2010
IEEE
111views Hardware» more  DSD 2010»
13 years 4 months ago
Faults Coverage Improvement Based on Fault Simulation and Partial Duplication
— A method how to improve the coverage of single faults in combinational circuits is proposed. The method is based on Concurrent Error Detection, but uses a fault simulation to f...
Jaroslav Borecky, Martin Kohlik, Hana Kubatova, Pa...
ISQED
2010
IEEE
156views Hardware» more  ISQED 2010»
13 years 7 months ago
On the design of different concurrent EDC schemes for S-Box and GF(p)
Recent studies have shown that an attacker can retrieve confidential information from cryptographic hardware (e.g. the secret key) by introducing internal faults. A secure and re...
Jimson Mathew, Hafizur Rahaman, Abusaleh M. Jabir,...
HPCA
2006
IEEE
14 years 6 months ago
BulletProof: a defect-tolerant CMP switch architecture
As silicon technologies move into the nanometer regime, transistor reliability is expected to wane as devices become subject to extreme process variation, particle-induced transie...
Kypros Constantinides, Stephen Plaza, Jason A. Blo...