34 search results - page 2 / 7 » ArchHDL: A Novel Hardware RTL Design Environment in C |
GECCO
2000
Springer
13 years 8 months ago
2000
Springer
This paper presents a novel evolvable hardware framework for the automated design of digital circuits for high performance applications. The technique evolves circuits correspondi...
FPGA
2007
ACM
13 years 11 months ago
2007
ACM
Chip-multiprocessors are quickly gaining momentum in all segments of computing. However, the practical success of CMPs strongly depends on addressing the difficulty of multithread...
DATE
2007
IEEE
13 years 11 months ago
2007
IEEE
This paper proposes an innovative methodology to perform and validate a Failure Mode and Effects Analysis (FMEA) at System-on-Chip (SoC) level. This is done in compliance with the...
DATE
2008
IEEE
13 years 11 months ago
2008
IEEE
This paper presents a novel cycle-approximate performance estimation technique for automatically generated transaction level models (TLMs) for heterogeneous multicore designs. The...
ITC
2003
IEEE
13 years 10 months ago
2003
IEEE
In a scan-based system with a large number of flip-flops, a major component of power is consumed during scanshift and clocking operation in test mode. In this paper, a novel scan-...