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» ArchHDL: A Novel Hardware RTL Design Environment in C
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RSP
2003
IEEE
149views Control Systems» more  RSP 2003»
13 years 10 months ago
Rapid Scheduling of Efficient VLSI Architectures for Next-Generation HSDPA
In this paper, an efficient design flow integrating Mentor Graphics Precesion C and HDL designer is derived. In this hybrid prototyping environment, efficient FPGA architectures a...
Yuanbin Guo, Gang Xu, Dennis McCain, Joseph R. Cav...
DATE
2008
IEEE
99views Hardware» more  DATE 2008»
13 years 11 months ago
Subsystem Exchange in a Concurrent Design Process Environment
This paper provides insight into the novel solutions used to build SoCs targeting increased productivity in a complex environment. Design of such SoCs relies on multi-team, multi-...
Marino Strik, Alain Gonier, Paul Williams
SC
2009
ACM
13 years 10 months ago
A framework for core-level modeling and design of reconfigurable computing algorithms
Reconfigurable computing (RC) is rapidly becoming a vital technology for many applications, from high-performance computing to embedded systems. The inherent advantages of custom-...
Gongyu Wang, Greg Stitt, Herman Lam, Alan D. Georg...
DATE
2004
IEEE
97views Hardware» more  DATE 2004»
13 years 9 months ago
A Formal Verification Methodology for Checking Data Integrity
Formal verification techniques have been playing an important role in pre-silicon validation processes. One of the most important points considered in performing formal verificati...
Yasushi Umezawa, Takeshi Shimizu
ISCAS
2005
IEEE
146views Hardware» more  ISCAS 2005»
13 years 11 months ago
A novel approach for network on chip emulation
— Current Systems-On-Chip execute applications that demand extensive parallel processing. Networks-On-Chip (NoC) provide a structured way of realizing interconnections on silicon...
Nicolas Genko, David Atienza, Giovanni De Micheli,...