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ISQED
2005
IEEE
108views Hardware» more  ISQED 2005»
13 years 11 months ago
Error Analysis for the Support of Robust Voltage Scaling
Recently, a new Dynamic Voltage Scaling (DVS) scheme has been proposed that increases energy efficiency significantly by allowing the processor to operate at or slightly below the...
David Roberts, Todd M. Austin, David Blaauw, Trevo...
MICRO
2007
IEEE
150views Hardware» more  MICRO 2007»
13 years 11 months ago
Leveraging 3D Technology for Improved Reliability
Aggressive technology scaling over the years has helped improve processor performance but has caused a reduction in processor reliability. Shrinking transistor sizes and lower sup...
Niti Madan, Rajeev Balasubramonian
ICPP
2008
IEEE
13 years 11 months ago
Optimizing Issue Queue Reliability to Soft Errors on Simultaneous Multithreaded Architectures
The issue queue (IQ) is a key microarchitecture structure for exploiting instruction-level and thread-level parallelism in dynamically scheduled simultaneous multithreaded (SMT) p...
Xin Fu, Wangyuan Zhang, Tao Li, José A. B. ...
DSN
2006
IEEE
13 years 11 months ago
Automatic Instruction-Level Software-Only Recovery
As chip densities and clock rates increase, processors are becoming more susceptible to transient faults that can affect program correctness. Computer architects have typically ad...
Jonathan Chang, George A. Reis, David I. August
MICRO
2009
IEEE
120views Hardware» more  MICRO 2009»
13 years 12 months ago
Tribeca: design for PVT variations with local recovery and fine-grained adaptation
With continued advances in CMOS technology, parameter variations are emerging as a major design challenge. Irregularities during the fabrication of a microprocessor and variations...
Meeta Sharma Gupta, Jude A. Rivers, Pradip Bose, G...