Tribeca: design for PVT variations with local recovery and fine-grained adaptation

With continued advances in CMOS technology, parameter variations are emerging as a major design challenge. Irregularities during the fabrication of a microprocessor and variations of voltage and temperature during its operation widen worst-case timing margins of the design—degrading performance significantly. Because runtime variations like supply voltage droops and temperature fluctuations depend on the activity signature of the processor’s workload, there are several opportunities to improve performance by dynamically adapting margins. This paper explores the powerperformance efficiency gains that result from designing for typical conditions while dynamically tuning frequency and voltage to accommodate the runtime behavior of workloads. Such a design depends on a fail-safe mechanism that allows it to protect against margin violations during adaptation; we evaluate several such mechanisms, and we propose a local recovery scheme that exploits spatial variation among the units o...

• Type: Conference
• Year: 2009
• Where: MICRO
• Authors: Meeta Sharma Gupta, Jude A. Rivers, Pradip Bose, Gu-Yeon Wei, David Brooks
• Keywords: Hardware, Ideal Processor, MICRO 2009, Parameter Variations, Voltage