39 search results - page 2 / 8 » Architectural Modifications to Enhance the Floating-Point Pe... |
FCCM
2003
IEEE
14 years 2 months ago
2003
IEEE
Most commercial and academic floating point libraries for FPGAs provide only a small fraction of all possible floating point units. In contrast, the floating point unit generat...
ISPAN
2005
IEEE
14 years 2 months ago
2005
IEEE
Within the parallel computing domain, field programmable gate arrays (FPGA) are no longer restricted to their traditional role as substitutes for application-specific integrated...
ASAP
2007
IEEE
13 years 11 months ago
2007
IEEE
This paper presents the enhancement of an ASIP’s floating point performance by coupling of a co-processor and adding of special instructions. Processor hardware modifications an...
ERSA
2010
13 years 7 months ago
2010
Cache-based, general purpose CPUs perform at a small fraction of their maximum floating point performance when executing memory-intensive simulations, such as those required for sp...
CORR
2008
Springer
13 years 9 months ago
2008
Springer
On modern architectures, the performance of 32-bit operations is often at least twice as fast as the performance of 64-bit operations. By using a combination of 32-bit and 64-bit ...