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ICCAD
2009
IEEE
118views Hardware» more  ICCAD 2009»
13 years 2 months ago
Memory organization and data layout for instruction set extensions with architecturally visible storage
Present application specific embedded systems tend to choose instruction set extensions (ISEs) based on limitations imposed by the available data bandwidth to custom functional un...
Panagiotis Athanasopoulos, Philip Brisk, Yusuf Leb...
GLVLSI
2007
IEEE
166views VLSI» more  GLVLSI 2007»
13 years 8 months ago
Efficient pipelining for modular multiplication architectures in prime fields
This paper presents a pipelined architecture of a modular Montgomery multiplier, which is suitable to be used in public key coprocessors. Starting from a baseline implementation o...
Nele Mentens, Kazuo Sakiyama, Bart Preneel, Ingrid...
ICASSP
2008
IEEE
13 years 11 months ago
Address assignment sensitive variable partitioning and scheduling for DSPS with multiple memory banks
Multiple memory banks design is employed in many high performance DSP processors. This architectural feature supports higher memory bandwidth by allowing multiple data memory acce...
Chun Jason Xue, Tiantian Liu, Zili Shao, Jingtong ...
VLSID
2002
IEEE
142views VLSI» more  VLSID 2002»
14 years 5 months ago
Address Code and Arithmetic Optimizations for Embedded Systems
An important class of problems used widely in both the embedded systems and scientific domains perform memory intensive computations on large data sets. These data sets get to be ...
J. Ramanujam, Satish Krishnamurthy, Jinpyo Hong, M...
DCC
2008
IEEE
14 years 4 months ago
The trace of an optimal normal element and low complexity normal bases
Let Fq be a finite field and consider an extension Fqn where an optimal normal element exists. Using the trace of an optimal normal element in Fqn , we provide low complexity norma...
Maria Christopoulou, Theodoulos Garefalakis, Danie...