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SPDP
1993
IEEE
13 years 8 months ago
Architectural Support for Block Transfers in a Shared-Memory Multiprocessor
This paper examines how the performance of a shared-memory multiprocessor can be improved by including hardware support for block transfers. A system similar to the Hector multipr...
Steven J. E. Wilton, Zvonko G. Vranesic
DATE
2005
IEEE
165views Hardware» more  DATE 2005»
13 years 10 months ago
Flexible Hardware/Software Support for Message Passing on a Distributed Shared Memory Architecture
With the advent of multi-processor systems on a chip, the interest for message passing libraries has revived. Message passing helps in mastering the design complexity of parallel ...
Francesco Poletti, Antonio Poggiali, Paul Marchal
HPCA
1999
IEEE
13 years 8 months ago
Comparative Evaluation of Fine- and Coarse-Grain Approaches for Software Distributed Shared Memory
Symmetric multiprocessors (SMPs) connected with low-latency networks provide attractive building blocks for software distributed shared memory systems. Two distinct approaches hav...
Sandhya Dwarkadas, Kourosh Gharachorloo, Leonidas ...
ASPLOS
1991
ACM
13 years 8 months ago
Performance Evaluation of Memory Consistency Models for Shared Memory Multiprocessors
The memory consistency model supported by a multiprocessor architecture determines the amount of buffering and pipelining that may be used to hide or reduce the latency of memory ...
Kourosh Gharachorloo, Anoop Gupta, John L. Henness...
ISCAS
2006
IEEE
157views Hardware» more  ISCAS 2006»
13 years 10 months ago
DCOS: cache embedded switch architecture for distributed shared memory multiprocessor SoCs
Abstract— Shared memory is a common inter-processor communication paradigm for on-chip multiprocessor SoC (MPSoC) platforms. The latency overhead of switch-based interconnection ...
Daewook Kim, Manho Kim, Gerald E. Sobelman