20 search results - page 2 / 4 » Architectural evaluation of 3D stacked RRAM caches |
ISCA
2009
IEEE
13 years 11 months ago
2009
IEEE
Caching techniques have been an efficient mechanism for mitigating the effects of the processor-memory speed gap. Traditional multi-level SRAM-based cache hierarchies, especially...
CF
2008
ACM
13 years 6 months ago
2008
ACM
The current methodology used in mass-market processor design is to create a single base microarchitecture (e.g., Intel's "Core"or AMD's"K8") that is ...
ICCAD
2007
IEEE
14 years 1 months ago
2007
IEEE
—In this paper, we introduce a novel reconfigurable architecture, named 3D nFPGA, which utilizes 3D integration techniques and new nanoscale materials synergistically. The propos...
ISCA
2006
IEEE
13 years 11 months ago
2006
IEEE
Long interconnects are becoming an increasingly important problem from both power and performance perspectives. This motivates designers to adopt on-chip network-based communicati...
ICPP
2007
IEEE
13 years 11 months ago
2007
IEEE
Three-dimensional Network-on-Chip (3-D NoC) is an emerging research topic exploring the network architecture of 3-D ICs that stack several smaller wafers for reducing wire length ...