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ASPLOS
1998
ACM
13 years 9 months ago
Space-Time Scheduling of Instruction-Level Parallelism on a Raw Machine
Advances in VLSI technology will enable chips with over a billion transistors within the next decade. Unfortunately, the centralized-resource architectures of modern microprocesso...
Walter Lee, Rajeev Barua, Matthew Frank, Devabhakt...
ISCA
1998
IEEE
134views Hardware» more  ISCA 1998»
13 years 9 months ago
Exploiting Fine-grain Thread Level Parallelism on the MIT Multi-ALU Processor
Much of the improvement in computer performance over the last twenty years has come from faster transistors and architectural advances that increase parallelism. Historically, par...
Stephen W. Keckler, William J. Dally, Daniel Maski...
IPPS
2005
IEEE
13 years 10 months ago
A Case Study on Pattern-Based Systems for High Performance Computational Biology
Computational biology research is now faced with the burgeoning number of genome data. The rigorous postprocessing of this data requires an increased role for high performance com...
Weiguo Liu, Bertil Schmidt
IPPS
2000
IEEE
13 years 9 months ago
MAJC-5200: A High Performance Microprocessor for Multimedia Computing
The newly introduced Microprocessor Architecture for Java Computing MAJC supports parallelism in a hierarchy of levels: multiprocessors on chip,vertical micro threading, instruct...
Subramania Sudharsanan
ISCA
1998
IEEE
151views Hardware» more  ISCA 1998»
13 years 9 months ago
Integrated Predicated and Speculative Execution in the IMPACT EPIC Architecture
Explicitly Parallel Instruction Computing (EPIC) architectures require the compiler to express program instruction level parallelism directly to the hardware. EPIC techniques whic...
David I. August, Daniel A. Connors, Scott A. Mahlk...