9 search results - page 1 / 2 » Architecture and DSP Implementation of a DVB-S2 Baseband Dem... |
DSD
2009
IEEE
13 years 11 months ago
2009
IEEE
—This paper presents the design and implementation of a baseband demodulator for DVB-S2 satellite receivers. In order to meet the requirements of different complex and multidomai...
IWSOC
2005
IEEE
13 years 10 months ago
2005
IEEE
A fully programmable radio baseband processor architecture is presented. The architecture is based on a DSP processor core and a number flexible accelerators, connected via a con...
DELTA
2006
IEEE
13 years 8 months ago
2006
IEEE
This paper describes the concept, architecture, development and demonstration of a real time, high performance, software defined 4-receiver system and a space time decoder to be i...
DATE
2000
IEEE
13 years 9 months ago
2000
IEEE
This paper presents a single chip implementation of a space-time algorithm for co-channel interference (CCI) and intersymbol interference (ISI) reduction in GSM/DCS systems. The t...
VTC
2006
IEEE
13 years 11 months ago
2006
IEEE
— In this paper we present extremely flexible and low power digital binary ASK, PSK, and FSK demodulator architectures for short-range applications that uses limiter amplifier (i...