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HOTI
2002
IEEE
13 years 9 months ago
Architecture and Hardware for Scheduling Gigabit Packet Streams
We present an architecture and hardware for scheduling gigabit packet streams in server clusters that combines a Network Processor datapath and an FPGA for use in server NICs and ...
Raj Krishnamurthy, Sudhakar Yalamanchili, Karsten ...
FCCM
2004
IEEE
112views VLSI» more  FCCM 2004»
13 years 8 months ago
ShareStreams: A Scalable Architecture and Hardware Support for High-Speed QoS Packet Schedulers
Raj Krishnamurthy, Sudhakar Yalamanchili, Karsten ...
PAM
2007
Springer
13 years 10 months ago
Packet Capture in 10-Gigabit Ethernet Environments Using Contemporary Commodity Hardware
Abstract. Tracing traffic using commodity hardware in contemporary highspeed access or aggregation networks such as 10-Gigabit Ethernet is an increasingly common yet challenging t...
Fabian Schneider, Jörg Wallerich, Anja Feldma...
SBACPAD
2003
IEEE
121views Hardware» more  SBACPAD 2003»
13 years 9 months ago
Optimizing Packet Capture on Symmetric Multiprocessing Machines
Traffic monitoring and analysis based on general purpose systems with high speed interfaces, such as Gigabit Ethernet and 10 Gigabit Ethernet, requires carefully designed software...
Gianluca Varenni, Mario Baldi, Loris Degioanni, Fu...
DATE
2008
IEEE
99views Hardware» more  DATE 2008»
13 years 11 months ago
GMDS: Hardware implementation of novel real output queuing architecture
In this paper, a real output queuing switch prototype implementation is presented. This implementation is based on a novel high speed multidrop backplane and a general purpose lin...
R. Arteaga, Félix Tobajas, Roberto Esper-Ch...