72 search results - page 1 / 15 » Architecture evaluation for power-efficient FPGAs |
FPGA
2003
ACM
13 years 10 months ago
2003
ACM
This paper presents a flexible FPGA architecture evaluation framework, named fpgaEVA-LP, for power efficiency analysis of LUT-based FPGA architectures. Our work has several contri...
FCCM
2009
IEEE
13 years 8 months ago
2009
IEEE
Most high-speed Internet Protocol (IP) lookup implementations use tree traversal and pipelining. Due to the available on-chip memory and the number of I/O pins of Field Programmab...
ISCAS
2005
IEEE
13 years 10 months ago
2005
IEEE
— Significant headway has been made in logic density and performance of FPGAs in the past decade. Power efficiency of FPGA architectures is arguably the next most important crite...
ASPDAC
1998
ACM
13 years 9 months ago
1998
ACM
We developed a new modular synthesis approach for design of low-power core-based data-intensive application-specific systems on silicon. The power optimization is conducted in th...
CAL
2006
13 years 4 months ago
2006
This paper evaluates asymmetric cluster chip multiprocessor (ACCMP) architectures as a mechanism to achieve the highest performance for a given power budget. ACCMPs execute serial ...